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general description the max1110/max1111 are low-power, 8-bit, 8-chan- nel analog-to-digital converters (adcs) that feature an internal track/hold, voltage reference, clock, and serial interface. they operate from a single +2.7v to +5.5v supply and consume only 85? while sampling at rates up to 50ksps. the max1110? 8 analog inputs and the max1111? 4 analog inputs are software-configurable, allowing unipolar/bipolar and single-ended/differential operation. successive-approximation conversions are performed using either the internal clock or an external serial-inter- face clock. the full-scale analog input range is deter- mined by the 2.048v internal reference, or by an externally applied reference ranging from 1v to v dd . the 4-wire serial interface is compatible with the spi, qspi, and microwire serial-interface standards. a serial-strobe output provides the end-of-conversion signal for interrupt-driven processors. the max1110/max1111 have a software-program- mable, 2? automatic power-down mode to minimize power consumption. using power-down, the supply current is reduced to 6? at 1ksps, and only 52? at 10ksps. power-down can also be controlled using the shdn input pin. accessing the serial interface automat- ically powers up the device. the max1110 is available in 20-pin ssop and dip packages. the max1111 is available in small 16-pin qsop and dip packages. ________________________applications portable data logging hand-held measurement devices medical instruments system diagnostics solar-powered remote systems 4?0ma-powered remote data-acquisition systems ____________________________features ? +2.7v to +5.5v single supply ? low power: 85? at 50ksps 6? at 1ksps ? 8-channel single-ended or 4-channel differential inputs (max1110) ? 4-channel single-ended or 2-channel differential inputs (max1111) ? internal track/hold; 50khz sampling rate ? internal 2.048v reference ? spi/qspi/microwire-compatible serial interface ? software-configurable unipolar or bipolar inputs ? total unadjusted error: ?lsb max ?.3lsb typ max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs ________________________________________________________________ maxim integrated products 1 input shift register control logic int clock output shift register +2.048v reference t/h analog input mux 8-bit sar adc in dout sstrb v dd dgnd agnd sclk din ch0 ch1 ch3 ch2 ch7* ch6* ch5* ch4* com refout *max1110 only refin out ref clock max1110 max1111 cs shdn ________________functional diagram 19-1194; rev 2; 10/98 part max1110 cpp max1110cap 0? to +70? 0? to +70? temp. range pin-package 20 plastic dip 20 ssop evaluation kit available ordering information ordering information continued at end of data sheet. * dice are specified at t a = +25?, dc parameters only. pin configurations appear at end of data sheet. for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 for small orders, phone 1-800-835-8769. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. max1110c/d 0? to +70? dice*
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd ..............................................................-0.3v to 6v agnd to dgnd .......................................................-0.3v to 0.3v ch0?h7, com, refin, refout to agnd ......................................-0.3v to (v dd + 0.3v) digital inputs to dgnd ...............................................-0.3v to 6v digital outputs to dgnd ............................-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70?) 16 plastic dip (derate 10.53mw/? above +70?) ......842mw 16 qsop (derate 8.30mw/? above +70?) ................667mw 16 cerdip (derate 10.00mw/? above +70?) ..........800mw 20 plastic dip (derate 11.11mw/? above +70?) ......889mw 20 ssop (derate 8.00mw/? above +70?) ................640mw 20 cerdip (derate 11.11mw/? above +70?) ..........889mw operating temperature ranges max1110c_p/max1111c_e................................0? to +70? max1110e_p/max1111e_e .............................-40? to +85? max1110mjp/max1111mje..........................-55? to +125? storage temperature range .............................-65? to +150? lead temperature (soldering, 10sec) .............................+300? electrical characteristics (v dd = +2.7v to +5.5v; unipolar input mode; com = 0v; f sclk = 500khz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1? capacitor at refout; t a = t min to t max ; unless otherwise noted.) -3db rolloff mhz 1.5 small-signal bandwidth khz 800 v ch_ = 2.048vp-p, 25khz (note 4) external reference, 2.048v v dd = 2.7v to 3.6v v dd = 2.7v to 3.6v no missing codes over temperature ?.35 ? conditions full-power bandwidth ? internal or external reference lsb gain error (note 3) db -75 channel-to-channel crosstalk db 68 sfdr spurious-free dynamic range db -70 thd total harmonic distortion (up to the 5th harmonic) ?.15 ?.5 lsb ?.1 channel-to-channel offset matching ppm/? ?.8 gain temperature coefficient lsb ? dnl differential nonlinearity units min typ max symbol parameter lsb ?.3 ? tue total unadjusted error bits 8 resolution db 49 sinad signal-to-noise and distortion ratio v dd = 5.5v (note 2) lsb ?.2 inl relative accuracy (note 1) v dd = 5.5v (note 2) lsb ?.5 offset error dc accuracy dynamic specifications (10.034khz sine-wave input, 2.048vp-p, 50ksps, 500khz external clock)
v max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +2.7v to +5.5v; unipolar input mode; com = 0v; f sclk = 500khz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1? capacitor at refout; t a = t min to t max ; unless otherwise noted.) on/off-leakage current, v ch_ = 0v or v dd used for data transfer only (note 6) external clock, 2mhz conditions ppm/? ?0 ma 3.5 refout short-circuit current pf 18 input capacitance ? ?.01 ? multiplexer leakage current 1 2 50 500 khz 400 internal clock frequency 0ma to 0.5ma output load mv 2.5 load regulation (note 8) ns 10 aperture delay ? 1 t acq track/hold acquisition time units min typ max symbol parameter ps v 1 v dd + 50mv input voltage range (note 9) ? 120 input current <50 aperture jitter external clock, 500khz, 10 clocks/conversion 20 internal clock ? 25 55 t conv conversion time (note 5) bipolar input, com = v refin / 2 unipolar input, com = 0v com v refin / 2 v 0v refin input voltage range, single- ended and differential (note 7) v 1.968 2.048 2.128 refout voltage external clock-frequency range mhz khz capacitive bypass at refout ? refout temperature coefficient v 2.7 5.5 v dd supply voltage 85 250 i dd supply current (note 2) v dd = 2.7v to 3.6v full-scale input c load = 10pf v dd = 2.7v to 3.6v; external reference, 2.048v; full-scale input mv ?.4 ? psr power-supply rejection (note 10) operating mode 2 ? power-down 3.2 10 software shdn at dgnd operating mode 120 250 v dd = 5.5v full-scale input c load = 10pf reference disabled reference disabled 45 80 conversion rate analog input internal reference external reference at refin power requirements
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +2.7v to +5.5v; unipolar input mode; com = 0v; f sclk = 500khz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1? capacitor at refout; t a = t min to t max ; unless otherwise noted.) cs = v dd (note 6) cs = v dd i source = 0.5ma i sink = 5ma shdn = open shdn = 0v or v dd (note 6) digital inputs = 0v or v dd shdn = open conditions pf 15 c out three-state output capacitance ? ?.01 ?0 i l three-state leakage current v v dd - 0.5 v oh output high voltage v 0.4 v ol output low voltage na ?00 shdn maximum allowed leakage for mid-input v v dd / 2 v flt shdn voltage, floating ? ? shdn input current v v dd - 0.4 v sh shdn input high voltage v 0.8 v il din, sclk, cs input low voltage v 1.1 v dd - 1.1 i sink = 16ma v sm 0.8 pf 15 c in din, sclk, cs input capacitance ? ? i in din, sclk, cs input leakage shdn input mid-voltage v 0.2 v hyst din, sclk, cs input hysteresis units min typ max symbol parameter v 0.4 v sl shdn input low voltage v dd 3.6v v dd > 3.6v v 2 v ih din, sclk, cs input high voltage 3 digital inputs: din, sclk, cs digital outputs: dout, sstrb shdn input
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs _______________________________________________________________________________________ 5 ns 100 t css figure 1, external clock mode only, c load = 100pf ns cs to sclk rise setup 240 figure 1, c load = 100pf ns 20 200 ns 0 t csh conditions cs to sclk rise hold 240 t dv cs fall to output enable figure 2, c load = 100pf ns 240 t tr cs rise to output disable t sdv cs fall to sstrb output enable (note 6) figure 2, external clock mode only, c load = 100pf ns 240 t str cs rise to sstrb output disable (note 6) figure 11, internal clock mode only ns 0 t sck sstrb rise to sclk rise (note 6) ns 200 t ch sclk pulse width high ns 200 t cl sclk pulse width low c load = 100pf ns 240 t sstrb sclk fall to sstrb ns 0 t dh din to sclk hold ? 1 t acq track/hold acquisition time ns 100 t ds din to sclk setup units min typ max symbol parameter timing characteristics (figures 8 and 9) (v dd = +2.7v to +5.5v, t a = t min to t max , unless otherwise noted.) note 1: relative accuracy is the analog value? deviation (at any code) from its theoretical value after the full-scale range is calibr ated. note 2: see typical operating characteristics. note 3: v refin = 2.048v, offset nulled. note 4: on-channel grounded; sine wave applied to all off-channels. note 5: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 6: guaranteed by design. not subject to production testing. note 7: common-mode range for the analog inputs is from agnd to v dd . note 8: external load should not change during the conversion for specified accuracy. note 9: external reference at 2.048v, full-scale input, 500khz external clock. note 10: measured as | v fs (2.7v) - v fs (3.6v) | . note 11: 1? at refout; internal reference settling to 0.5lsb. ns 20 240 t do sclk fall to output data valid figure 1, c load = 100pf max111_c/e max111_m external reference 20 internal reference (note 11) ? 12 t wake wake-up time ms
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs 6 _______________________________________________________________________________________ __________________________________________typical operating characteristics (v dd = +2.7v; f sclk = 500khz; external clock (50% duty cycle); r l = ; t a = +25?, unless otherwise noted.) 400 100 2.5 6.0 supply current vs. supply voltage 150 350 max1110-01 supply voltage (v) supply current ( m a) 3.0 3.5 4.0 4.5 5.0 5.5 300 250 200 output code = 10101010 c load = 60pf c load = 30pf 160 60 -60 140 supply current vs. temperature 80 140 max1110-02 temperature (?) supply current ( m a) -20 20 60 100 120 100 output code = full scale c load = 10pf v dd = 5.5v v dd = 3.6v 5.0 2.0 -60 140 shutdown supply current vs. temperature 2.5 4.5 max1110-03 temperature (?) shutdown supply current ( m a) -20 20 60 100 4.0 3.5 3.0 shdn = dgnd 0.8 0 2.5 6.0 offset error vs. supply voltage 0.1 0.7 0.6 max1110-04 supply voltage (v) offset error (lsb) 3.0 3.5 4.0 4.5 5.0 5.5 0.5 0.4 0.3 0.2 0.5 0 2.5 6.0 integral nonlinearity vs. supply voltage 0.1 0.4 max1110-05 supply voltage (v) inl (lsb) 3.0 3.5 4.0 4.5 5.0 5.5 0.3 0.2 0.3 -0.3 0 256 differential nonlinearity vs. code -0.2 0.2 0.1 max1110-06 digital code dnl (lsb) 64 128 192 0 -0.1 0.6 0 -60 140 offset error vs. temperature 0.1 0.2 0.5 max1110-07 temperature (?) offset error (lsb) -20 20 60 100 0.4 0.3 0.20 -0.20 0 256 integral nonlinearity vs. code -0.10 -0.15 0.15 0.10 0.05 max1110-08 digital code inl (lsb) 64 128 192 0 -0.05 20 -100 025 fft plot -80 -20 0 max1110-09 frequency (khz) amplitude (db) 5 101520 -60 -40 f ch_ = 10.034khz, 2vp-p f sample = 50ksps
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs _______________________________________________________________________________________ 7 ______________________________________________________________pin description 16 sstrb serial-strobe output. in internal clock mode, sstrb goes low when the max1110/ max1111 begin the a/d conversion and goes high when the conversion is done. in external clock mode, sstrb pulses high for two clock periods before the msb is shifted out. high impedance when cs is high (external clock mode only). 20 v dd positive supply voltage, +2.7v to +5.5v 18 cs active-low chip select. data is not clocked into din unless cs is low. when cs is high, dout is high impedance. the voltage at cs may exceed v dd (up to 5.5v). 19 sclk serial-clock input. clocks data in and out of serial interface. in external clock mode, sclk also sets the conversion speed (duty cycle must be 45% to 55%). the voltage at sclk may exceed v dd (up to 5.5v). 17 din serial-data input. data is clocked in at sclk? rising edge. the voltage at din may exceed v dd (up to 5.5v). 12 refout internal reference generator output. bypass with a 1? capacitor to agnd. 14 dgnd digital ground 15 dout serial-data output. data is clocked out on sclk? falling edge. high impedance when cs is high. 13 agnd analog ground 10 shdn three-level shutdown input. normally floats. pulling shdn low shuts the max1110/ max1111 down to 10? (max) supply current; otherwise, the devices are fully opera- tional. pulling shdn high shuts down the internal reference. 11 refin reference voltage input for analog-to-digital conversion. connect to refout to use the internal reference. 5? ch4?h7 sampling analog inputs 1? ch0?h3 sampling analog inputs +3v 3k c load dgnd dout c load dgnd 3k dout a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol figure 1. load circuits for enable time +3v 3k c load dgnd dout c load dgnd 3k dout a) v oh to high-z b) v ol to high-z figure 2. load circuits for disable time 12 16 14 15 13 8 10 11 9 6 7 1? 5 9 com ground reference for analog inputs. sets zero-code voltage in single-ended mode. must be stable to ?.5lsb. pin max1111 name function max1110
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs 8 _______________________________________________________________________________________ _______________detailed description the max1110/max1111 analog-to-digital converters (adcs) use a successive-approximation conversion technique and input track/hold (t/h) circuitry to convert an analog signal to an 8-bit digital output. a flexible seri- al interface provides easy interface to microprocessors (?s). figure 3 shows the typical operating circuit. pseudo-differential input the sampling architecture of the adc? analog com- parator is illustrated in figure 4, the equivalent input cir- cuit. in single-ended mode, in+ is internally switched to the selected input channel, ch_, and in- is switched to com. in differential mode, in+ and in- are selected from the following pairs: ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7. configure the max1110 channels with table 1 and the max1111 channels with table 2. in differential mode, in- and in+ are internally switched to either of the analog inputs. this configuration is pseudo-differential to the effect that only the signal at in+ is sampled. the return side (in-) must remain sta- ble within ?.5lsb (?.1lsb for best results) with respect to agnd during a conversion. to accomplish this, connect a 0.1? capacitor from in- (the selected analog input) to agnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acquisition interval spans two sclk cycles and ends on the falling sclk edge after the last bit of the input control word has been entered. at the end of the acqui- sition interval, the t/h switch opens, retaining charge on c hold as a sample of the signal at in+. the conver- sion interval begins with the input multiplexer switching c hold from the positive input (in+) to the negative input (in-). in single-ended mode, in- is simply com. this unbalances node zero at the input of the com- parator. the capacitive dac adjusts during the remain- der of the conversion cycle to restore node zero to 0v within the limits of 8-bit resolution. this action is equiva- lent to transferring a charge of 18pf x (v in+ - v in- ) from c hold to the binary-weighted capacitive dac, which in turn forms a digital representation of the analog input signal. track/hold the t/h enters its tracking mode on the falling clock edge after the sixth bit of the 8-bit control byte has been shifted in. it enters its hold mode on the falling clock edge after the eighth bit of the control byte has been shifted in. if the converter is set up for single- ended inputs, in- is connected to com, and the con- verter samples the ??input; if it is set up for differential inputs, in- connects to the ??input, and the difference (in+ - in-) is sampled. at the end of the conversion, the positive input connects back to in+, and c hold charges to the input signal. v dd i/o sck (sk) mosi (so) miso (si) v ss shdn sstrb dout din sclk cs com dgnd agnd v dd ch7 1 m f 0.1 m f 1 m f ch0 analog inputs max1110 max1111 cpu +2.7v refin refout figure 3. typical operating circuit ch0 ch1 ch2 ch3 ch4* ch5* ch6* ch7* com c switch track t/h switch c hold hold capacitive dac refin zero comparator + 18pf 6.5k r in single-ended mode: in+ = cho?h7, in- = com. differential mode: in+ and in- selected from pairs of ch0/ch1, ch2/ch3, ch4*/ch5*, ch6*/ch7*. *max1110 only at the sampling instant, the mux input switches from the selected in+ channel to the selected in- channel. input mux figure 4. equivalent input circuit
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs _______________________________________________________________________________________ 9 table 1a. max1110 channel selection in single-ended mode (sgl/ dif = 1) table 1b. max1110 channel selection in differential mode (sgl/ dif = 0) table 2a. max1111 channel selection in single-ended mode (sgl/ dif = 1) table 2b. max1111 channel selection in differential mode (sgl/ dif = 0) + 1 1 1 + 1 ch2 1 0 + 0 ch3 1 1 + 0 ch1 1 0 + 1 + ch0 0 1 + 1 0 0 + 0 0 1 com ch7 ch6 sel2 ch5 ch4 0 0 0 sel0 sel1 + 1 1 1 + 0 ch2 1 1 + 1 ch3 0 1 + 0 ch1 0 1 + 1 + ch0 1 0 + 0 1 0 + 1 0 0 ch7 ch6 sel2 ch5 ch4 0 0 0 sel0 sel1 + x 1 1 + x ch1 1 0 + ch0 + x 0 1 sel2 ch3 ch2 x 0 0 sel0 sel1 + x 1 1 + x ch1 0 1 + ch0 + x 1 0 sel2 ch3 ch2 x 0 0 sel0 sel1 com
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs 10 ______________________________________________________________________________________ table 3. control-byte format start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) name sgl/ dif 2 bit 1 = single ended, 0 = differential. selects single-ended or differential conversions. in single- ended mode, input signal voltages are referred to com. in differential mode, the voltage differ- ence between two channels is measured. see tables 1 and 2. description uni/ bip 3 start 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. select differential operation if bipolar mode is used. see table 4. pd0 0 (lsb) 7 (msb) 1 = external clock mode, 0 = internal clock mode. selects external or internal clock mode. the first logic 1 ?bit after cs goes low defines the beginning of the control byte. sel2 sel1 sel0 6 5 4 select which of the input channels are to be used for the conversion (tables 1 and 2). pd1 1 1 = fully operational, 0 = power-down. selects fully operational or power-down mode. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. the acquisition time, t acq , is the minimum time needed for the signal to be acquired. it is calculated by: t acq = 6 x (r s + r in ) x 18pf where r in = 6.5k , r s = the source impedance of the input signal, and t acq is never less than 1?. note that source impedances below 2.4k do not significantly affect the ac performance of the adc. input bandwidth the adc? input tracking circuitry has a 1.5mhz small- signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high- frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog inputs internal protection diodes, which clamp the analog input to v dd and agnd, allow the channel input pins to swing from (agnd - 0.3v) to (v dd + 0.3v) without dam- age. however, for accurate conversions near full scale, the inputs must not exceed v dd by more than 50mv or be lower than agnd by 50mv. if the analog input exceeds 50mv beyond the sup- plies, do not forward bias the protection diodes of off channels over 2ma. the max1110/max1111 can be configured for differen- tial or single-ended inputs with bits 2 and 3 of the con- trol byte (table 3). in single-ended mode, the analog inputs are internally referenced to com with a full-scale input range from com to v refin + com. for bipolar operation, set com to v refin / 2. in differential mode, choosing unipolar mode sets the differential input range at 0v to v refin . in unipolar mode, the output code is invalid (code zero) when a negative differential input voltage is applied. bipolar mode sets the differential input range to ? refin / 2. note that in this mode, the common-mode input range includes both supply rails. refer to table 4 for input voltage ranges. quick look to quickly evaluate the max1110/max1111? analog performance, use the circuit of figure 5. the max1110/max1111 require a control byte to be written to din before each conversion. tying din to +3v feeds
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs ______________________________________________________________________________________ 11 in control bytes of $ff (hex), which trigger single- ended, unipolar conversions on ch7 (max1110) or ch3 (max1111) in external clock mode without power- ing down between conversions. in external clock mode, the sstrb output pulses high for two clock periods before the most significant bit of the 8-bit conversion result is shifted out of dout. varying the analog input alters the output code. a total of 10 clock cycles is required per conversion. all transitions of the sstrb and dout outputs occur on sclk? falling edge. how to start a conversion a conversion is started by clocking a control byte into din. with cs low, each rising edge on sclk clocks a bit from din into the max1110/max1111? internal shift reg- ister. after cs falls, the first arriving logic ??bit at din defines the msb of the control byte. until this first start bit arrives, any number of logic ??bits can be clocked into din with no effect. table 3 shows the control-byte format. the max1110/max1111 are compatible with microwire, spi, and qspi devices. for spi, select the correct clock polarity and sampling edge in the spi control registers: set cpol = 0 and cpha = 0. microwire, spi, and qspi all transmit a byte and receive a byte at the same time. using the typical operating circuit (figure 3), the simplest software interface requires three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the adc, and two more 8-bit transfers to clock out the 8-bit conversion result). figure 6 shows the max1110/ max1111 common serial-interface connections. 1? 0.1? v dd dgnd agnd cs sclk din dout sstrb shdn +3v n.c. 0.01? ch7 (ch3) com refout refin c1 1? 0v to +2.048v analog input oscilloscope ch1 ch2 ch3 ch4 *full-scale analog input, conversion result = $ff (hex) ( ) are for the max1111. max1110 max1111 +3v 500khz oscillator sclk sstrb dout* figure 5. quick-look circuit table 4. full-scale and zero-scale voltages unipolar mode v refin + com +v refin / 2 + com full scale com com -v refin / 2 + com positive full scale zero scale zero scale bipolar mode negative full scale
simple software interface make sure the cpu? serial interface runs in master mode so the cpu generates the serial clock. choose a clock frequency from 50khz to 500khz. 1) set up the control byte for external clock mode and call it tb1. tb1 should be of the format 1xxxxx11 binary, where the xs denote the particular channel and conversion mode selected. 2) use a general-purpose i/o line on the cpu to pull cs low. 3) transmit tb1 and, simultaneously, receive a byte and call it rb1. ignore rb1. 4) transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte rb2. 5) transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte rb3. 6) pull cs high. figure 7 shows the timing for this sequence. bytes rb2 and rb3 contain the result of the conversion padded with two leading zeros and six trailing zeros. the total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. make sure that the total conversion time does not exceed 1ms, to avoid excessive t/h droop. digital inputs cs , sclk, and din can accept input signals up to 5.5v, regardless of the supply voltages. this allows the max1110/max1111 to accept digital inputs from both 3v and 5v systems. max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs 12 ______________________________________________________________________________________ sstrb cs sclk din dout 14 8 12 16 20 24 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b7 b6 b5 b4 b3 b2 b1 b0 acquisition (f sclk = 500khz) idle filled with zeros idle conversion t acq a/d state rb1 rb2 rb3 4 m s figure 7. single-conversion timing, external clock mode, 24 clocks cs sclk dout i/o sck miso +3v ss a) spi cs sclk dout cs sck miso +3v ss b) qspi max1110 max1111 max1110 max1111 max1110 max1111 cs sclk dout i/o sk si c) microwire figure 6. common serial-interface connections to the max1110/max1111
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs ______________________________________________________________________________________ 13 digital output in unipolar input mode, the output is straight binary (figure 15). for bipolar inputs, the output is two?-com- plement (figure 16). data is clocked out at sclk? falling edge in msb-first format. clock modes the max1110/max1111 can use either an external ser- ial clock or the internal clock to perform the successive- approximation conversion. in both clock modes, the external clock shifts data in and out of the devices. bit pd0 of the control byte programs the clock mode. figures 8?1 show the timing characteristics common to both modes. external clock in external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital conversion steps. sstrb pulses high for two clock periods after the last bit of the control byte. successive- approximation bit decisions are made and appear at dout on each of the next eight sclk falling edges (figure 7). after the eight data bits are clocked out, subsequent clock pulses clock out zeros from the dout pin. sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb outputs a logic low. figure 9 shows the sstrb timing in external clock mode. the conversion must complete in 1ms, or droop on the sample-and-hold capacitors may degrade conversion results. use internal clock mode if the serial-clock fre- quency is less than 50khz, or if serial-clock interruptions could cause the conversion interval to exceed 1ms. cs sclk din dout t csh t css t cl t ds t dh t dv t do t ch t do t tr t csh figure 8. detailed serial-interface timing t sdv t sstrb pd0 clocked in t str sstrb sclk cs t sstrb figure 9. external clock mode sstrb detailed timing
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs 14 ______________________________________________________________________________________ sstrb cs sclk din dout 14 8 12 15 17 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b7 b6 b1 b0 t acq 4? (f sclk = 500khz) idle filled with zeros idle conversion 25? typ a/d state 2 3 5 6 7 9 10 11 16 18 t conv figure 10. internal clock mode timing pd0 clock in t sstrb t csh t conv t sck sstrb sclk t css note: for best noise performance, keep sclk low during conversion. cs figure 11. internal clock mode sstrb detailed timing internal clock internal clock mode frees the ? from the burden of running the sar conversion clock. this allows the con- version results to be read back at the processor? con- venience, at any clock rate up to 2mhz. sstrb goes low at the start of the conversion and then goes high when the conversion is complete. sstrb is low for 25? (typically), during which time sclk should remain low for best noise performance. an internal register stores data when the conversion is in progress. sclk clocks the data out of this register at any time after the conversion is complete. after sstrb goes high, the second falling clock edge produces the msb of the conversion at dout, followed by the remaining bits in msb-first format (figure 10). cs does not need to be held low once a conversion is started. pulling cs high prevents data from being clocked into the max1110/max1111 and three-states dout, but it does not adversely affect an internal clock-mode con- version already in progress. when internal clock mode is selected, sstrb does not go into a high-impedance state when cs goes high. figure 11 shows the sstrb timing in internal clock mode. in this mode, data can be shifted in and out of the max1110/max1111 at clock rates up to 2mhz, pro- vided that the minimum acquisition time, t acq , is kept above 1?.
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs ______________________________________________________________________________________ 15 sclk din dout cs s control byte 0 control byte 1 s conversion result 0 b7 b0 b7 b0 b7 conversion result 1 conversion result 2 sstrb control byte 2 s 1 888 10 1 10 1 10 1 control byte 3 s figure 12a. continuous conversions, external clock mode, 10 clocks/conversion timing cs sclk din dout s control byte 0 control byte 1 s conversion result 0 b7 b0 b7 conversion result 1 figure 12b. continuous conversions, external clock mode, 16 clocks/conversion timing data framing the falling edge of cs does not start a conversion. the first logic high clocked into din is interpreted as a start bit and defines the first bit of the control byte. a conver- sion starts on the falling edge of sclk, after the eighth bit of the control byte (the pd0 bit) is clocked into din. the start bit is defined as: the first high bit clocked into din with cs low any time the converter is idle; e.g., after v dd is applied. or the first high bit clocked into din after the msb of a conversion in progress is clocked onto the dout pin. if cs is toggled before the current conversion is com- plete, then the next high bit clocked into din is recog- nized as a start bit; the current conversion is terminated, and a new one is started. the fastest the max1110/max1111 can run is 10 clocks per conversion. figure 12a shows the serial- interface timing necessary to perform a conversion every 10 sclk cycles in external clock mode. many microcontrollers require that conversions occur in multiples of eight sclk clocks; 16 clocks per conver- sion is typically the fastest that a microcontroller can drive the max1110/max1111. figure 12b shows the serial-interface timing necessary to perform a conver- sion every 16 sclk cycles in external clock mode.
applications information power-on reset when power is first applied, and if shdn is not pulled low, internal power-on reset circuitry activates the max1110/max1111 in internal clock mode. sstrb is high on power-up and, if cs is low, the first logical 1 on din is interpreted as a start bit. until a conversion takes place, dout shifts out zeros. no conversions should be performed until the reference voltage has stabilized (see electrical characteristics ). power-down when operating at speeds below the maximum sam- pling rate, the max1110/max1111? automatic power- down mode can save considerable power by placing the converters in a low-current shutdown state between conversions. figure 13 shows the average supply cur- rent as a function of the sampling rate. select power-down with pd1 of the din control byte with shdn high or floating (table 3). pull shdn low at any time to shut down the converters completely. shdn overrides pd1 of the control byte. figures 14a and 14b illustrate the various power-down sequences in both external and internal clock modes. software power-down software power-down is activated using bit pd1 of the control byte. when software power-down is asserted, the adcs continue to operate in the last specified clock mode until the conversion is complete. the adcs then power down into a low quiescent-current state. in internal clock mode, the interface remains active, and conversion results may be clocked out after the max1110/ max1111 have entered a software power-down. the first logical 1 on din is interpreted as a start bit, which powers up the max1110/max1111. if the din byte contains pd1 = 1, then the chip remains powered up. if pd1 = 0, power-down resumes after one conversion. hard-wired power-down pulling shdn low places the converters in hard-wired power-down. unlike software power-down, the conver- sion is not completed; it stops coincidentally with shdn being brought low. shdn also controls the state of the internal reference (table 5). letting shdn float enables the internal 2.048v voltage reference. when returning to normal operation with shdn floating, there is a t rc delay of approximately 1m x c load , where c load is the capacitive loading on the shdn pin. pulling shdn high disables the internal reference, which saves power when using an external reference. external reference an external reference between 1v and v dd should be connected directly at the refin terminal. the dc input impedance at refin is extremely high, consisting of leakage current only (typically 10na). during a conver- sion, the reference must be able to deliver up to 20? average load current and have an output impedance of 1k or less at the conversion clock frequency. if the reference has higher output impedance or is noisy, bypass it close to the refin pin with a 0.1? capacitor. if an external reference is used with the max1110/ max1111, tie shdn to v dd to disable the internal refer- ence and decrease power consumption. max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs 16 ______________________________________________________________________________________ table 5. hard-wired power-down and internal reference state shdn state device mode 1 enabled floating enabled 0 power-down internal reference disabled disabled enabled 1000 1 010 30 50 10 100 max1110-fig13 sampling rate (ksps) supply current ( m a) 20 40 v dd = v refin = 3v c load at dout and sstrb c load = 30pf code = 11111111 c load = 30pf code = 10101010 c load = 60pf code = 10101010 figure 13. average supply current vs. sampling rate
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs ______________________________________________________________________________________ 17 internal reference to use the max1110/max1111 with the internal refer- ence, connect refin to refout. the full-scale range of the max1110/max1111 with the internal reference is typically 2.048v with unipolar inputs, and ?.024v with bipolar inputs. the internal reference should be bypassed to agnd with a 1? capacitor placed as close to the refin pin as possible. transfer function table 4 shows the full-scale voltage ranges for unipolar and bipolar modes. figure 15 depicts the nominal, unipo- lar i/o transfer function, and figure 16 shows the bipolar i/o transfer function when using a 2.048v reference. code transitions occur at integer lsb values. output cod- ing is binary, with 1lsb = 8mv (2.048v/256) for unipolar operation and 1lsb = 8mv [(2.048v/2 - -2.048v/2)/256] for bipolar operation. powered up power- down powered up powered up data valid data valid data invalid external external internal sx xxxx 11 s 01 xx x x x xx xxx s11 power- down mode dout din clock mode shdn sets external clock mode sets external clock mode sets power- down mode figure 14a. power-down modes, external clock timing diagram power-down powered up powered up data valid data valid internal clock mode sx xxxx 10 s 00 xx x x x s mode dout din sets internal clock mode sets power-down mode conversion conversion sstrb figure 14b. power-down modes, internal clock timing diagram
layout, grounding, and bypassing for best performance, use printed circuit boards. wire- wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digi- tal (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 17 shows the recommended system ground connections. a single-point analog ground (star ground point) should be established at agnd, separate from the logic ground. connect all other analog grounds and dgnd to the star ground. no other digital system ground should be connected to this ground. the ground return to the power supply for the star ground should be low impedance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply may affect the comparator in the adc. bypass the supply to the star ground with 0.1? and 1? capacitors close to the v dd pin of the max1110/max1111. minimize capacitor lead lengths for best supply-noise rejection. if the +3v power supply is very noisy, a 10 resistor can be connected to form a lowpass filter. max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs 18 ______________________________________________________________________________________ +3v gnd supplies dgnd +3v dgnd agnd v dd digital circuitry max1110 max1111 r* = 10 w * optional figure 17. power-supply grounding connections 01111111 output code 01111110 00000010 00000001 00000000 11111111 11111110 11111101 10000001 10000000 -fs com input voltage (lsb) +fs - 1 lsb 2 +fs = v refin + com 2 -fs = -v refin + com 2 com = v refin 2 1lsb = v refin 256 figure 16. bipolar transfer function output code full-scale transition 11111111 11111110 11111101 00000011 00000010 00000001 00000000 123 0 fs fs - 1lsb fs = v refin + com 1lsb = v refin 256 input voltage (lsb) (com) figure 15. unipolar transfer function
max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs ______________________________________________________________________________________ 19 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 v dd sclk cs din ch3 ch2 ch1 ch0 top view sstrb dout dgnd agnd ch7 ch6 ch5 ch4 12 11 9 10 refout refin shdn com max1110 dip/ssop 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v dd sclk cs din sstrb dout dgnd agnd ch0 ch1 ch2 ch3 com shdn refin refout max1111 dip/qsop pin configurations chip information ordering information (continued) part max1110eap max1110mjp -55? to +125? -40? to +85? temp. range pin-package 20 ssop 20 cerdip** ** contact factory for availability. transistor count: 1996 substrate connected to dgnd max1110epp -40? to +85? 20 plastic dip max1111 cpe max1111epe max1111eee -40? to +85? -40? to +85? 0? to +70? 16 plastic dip 16 plastic dip 16 qsop max1111cee 0? to +70? 16 qsop max1111mje -55? to +125? 16 cerdip**
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1998 maxim integrated products printed usa is a registered trademark of maxim integrated products. max1110/max1111 +2.7v, low-power, multichannel, serial 8-bit adcs ________________________________________________________package information qsop.eps ssop.eps

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